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Processor: Cache Memory
Katana
®
752i User’s Manual 10006024-04
4-12
L2DO: L2 Data-Only.
Setting this bit inhibits the caching of instructions in the L2 cache. All accesses from the L2
instruction cache are treated as cache-inhibited by the L2 cache.
L2I: L2 global Invalidate.
Setting this bit invalidates the L2 cache globally by clearing the L2 status bits.
L2WT: L2 Write-Through.
Setting this bit selects write-through mode (rather than default copy-back mode) so all
writes to the L2 cache also write through to the 60x bus.
L2TS: L2 Test Support.
Setting this bit causes cache block pushes from the L1 data cache that result from dcbf and
dcbst instructions to be written only into the L2 cache and marked valid. Also causes single-
beat store operations that miss in the L2 cache to be discarded.
L2L0CKLO: L2 cache locking: lock ways 0 and 1.
L2LOCKHI: L2 cache locking: lock ways 2 and 3.
SHEE: Snoop Hit in locked line Error Enable.
SHERR: Snoop Hit in locked line Error.
L2LOCK0: Lock way 0 if either bit 20 or bit 24 is set to one.
L2LOCK1: Lock way 1 if either bit 20 or bit 25 is set to one.
L2LOCK2: Lock way 2 if either bit 21 or bit 26 is set to one.
L2LOCK3: Lock way 3 if either bit 21 or bit 27 is set to one.
L2IO: L2 Instruction-Only.
Setting this bit inhibits data caching in the L2 cache.
L2IP: L2 global Invalidate in Progress.
This read only bit indicates whether an L2 global invalidate is occurring.
The L2 cache is disabled following a power-on or hard reset. Before enabling the L2 cache,
configuration parameters must be set in the L2CR and the L2 tags must be globally invali-
dated. Initialize the L2 cache during system start-up per the following sequence:
1 Power-on reset (automatically performed by the assertion of HRESET* signal).
2 Disable interrupts and dynamic power management (DPM).
3 Disable L2 cache by clearing L2CR[L2E].
4 Perform an L2 global invalidate.
5 Enable the L2 cache for normal operation by setting the L2CR[L2E] bit to 1.