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10006024-04 Katana
®
752i User’s Manual
6-1
Section 6
Device Bus PLD
The processor complex on the Katana
®
752i has a programmable logic device (PLD) that
provides control logic for the 750GL device bus. This PLD implements various registers
relating to reset control, interrupt handling, product identification, PCI enumeration, and
board configuration. This chapter describes the registers in the device bus PLD, which is
also known as the MVC PLD.
RESET REGISTERS
The device bus PLD routes and distributes the reset signals. Two registers support this func-
tionality. The read-only Reset Event register at hex location F820,0000
16
indicates the rea-
son for the last reset as follows.
Register 6-1: Reset Event
InitAct: Initialization Active:
Set to 1 when the MV64460 InitAct pin does not go inactive after reset
WD: Watchdog:
Set to 1 when a reset was caused by the expiration of the MV64460 watchdog timer
COPS: Soft Reset:
Set to 1 when a COP header soft reset (SRESET) has occurred
COPH: Hard Reset:
Set to 1 when a COP header hard reset (HRESET) has occurred
PMCR: PMC Reset:
Set to 1 when a PPMC issues a PMC Reset Out
CPCI: CPCI:
Set to 1 when a cPCI reset (RST* signal) has occurred
FP: Front Panel:
Set to 1 when the front panel switch caused a reset
The Reset Command register at hex location F820,1000
16
forces one of several types of
resets, as shown below. After a reset sequence is initiated by writing a one to a valid bit, the
bit is automatically cleared.
Note: When writing to this register, only set one bit at a time.
76543210
InitAct Reserved WD COPS COPH PMCR CPCI FP