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System Controller: SDRAM Controller
10006024-04 Katana
®
752i User’s Manual
5-3
1 Read the CPU Configuration register. This guarantees that all previous transactions in the
CPU interface pipe are flushed.
2 Program the register to its new value.
3 Read polling of the register until the new data is being read.
Caution: Setting the CPU Configuration register must be done only once. For example, if the CPU
interface is configured to support Out of Order (OOO) read completion, changing the
register to not support OOO read completion is fatal.
SDRAM CONTROLLER
The MV64460 supports double data rate (DDR) synchronous dynamic random access
memory (SDRAM). The SDRAM controller supports up to four banks of SDRAMs. It has a 16-
bit address bus (M_DA[13:0] and M_BA[1:0]) and a 72-bit data bus (M_DQ[63:0] and
M_CB7[7:0]). The SDRAM controller supports both registered and unbuffered SDRAM
devices. Other features include:
• 64-bit wide (+ 8-bit ECC) SDRAM interface
• Up to 200-MHz SDRAM frequency
• Support for 64-megabit to one-gigabit DDR SDRAM devices
• Supports both physical and virtual bank interleaving
The MV64460 has a number of SDRAM registers. Refer to the Marvell web site for available
documentation.
DEVICE CONTROLLER INTERFACE
The device controller supports up to five banks of devices. Each bank’s supported memory
space can be programmed separately in one megabyte quantities up to 512 megabytes of
address space with a total device space of 2.5 gigabytes. Other features include:
• Dedicated 32-bit multiplexed address/data bus (separate from the SDRAM bus)
• 66 MHz bus frequency
• Five chip selects, each with programmable timing
• Use as a high bandwidth interface to user specific logic
• Supports many types of standard memory and I/O devices
Each bank has its own parameter register and can be programmed to 8, 16, or 32-bits wide.
The device interface consists of 128 bytes of write buffer and 128 bytes of read buffer.
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