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Processor: Exception Processing
Katana
®
752i User’s Manual 10006024-04
4-10
FP: Floating-Point available. This bit is set on initial power-up.
0= Prevents floating-point instructions dispatch (loads, stores, moves).
1= Executes floating-point instructions.
ME: Machine check Enable.
0= Machine check exceptions disabled.
1= Machine check exceptions enabled.
FE0/FE1: These bits define the Floating-point Exception mode.
Table 4-5: Floating Point Exception Mode Bits
SE: Single-step trace Enable.
0= Executes instructions normally.
1= Single-step trace exception generated.
BE: Branch trace Enable.
0= Executes instructions normally.
1= Branch type trace exception generated.
IP: Exception Prefix. Initially, this bit is cleared so that the exception vector table is placed at
the base of RAM (0000,0000
16
). When this bit is set, the vector table is placed at the base of
ROM (FFF0,0000
16
).
IR/DR: Instruction and Data address translation enables.
0= Address translation disabled.
1= Address translation enabled.
PM: Marks a process for the Performance Monitor.
0= Process is not marked.
1= Process is marked.
RI: Recoverable exception enable for system reset and machine check. This feature is enabled
on initial power-up.
0= Exception is not recoverable.
1= Exception is recoverable.
LE: Little-endian mode enable.
0= Big-endian mode (default).
1= Little-endian mode.
FE0: FE1: FP Exception Mode:
00Disabled
0 1 Imprecise nonrecoverable
1 0 Imprecise recoverable
11Precise