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Intel® Server Board SE7520JR2 Error Reporting and Handling
Revision 1.0
C78844-002
153
The following table shows memory error handling with both a mBMC and Sahalee BMC.
Table 57: Memory Error Handling mBMC vs Sahalee
Memory with RAS
mode
Server with mBMC Server with IMM Sahalee BMC
Sparing mode /
Mirroring mode
When Sparing or Mirroring occurs:
- BIOS will not report memory
RAS configuration to mBMC.
- BIOS will light the faulty DIMM
LED.
DIMMs which go off line during
OS runtime will be back online on
the next system reboot without
user intervention.
Sparing and Mirroring states are
not sticky across system reset.
When Sparing or Mirroring occurs:
- BIOS will report memory RAS
configuration to BMC.
- BIOS will light the faulty DIMM LED.
DIMMs which go off line during OS
runtime will not be back online on the
next system reboot.
Sparing and Mirroring states are
sticky across system reset.
Setting “Memory Retest” option in
BIOS Setup will re-enable off-line
DIMMs.
Note: BIOS does not support Memory Data Scrubber Error.
6.2.2 Memory Error Handling in non-RAS Mode
If memory RAS features are not enabled in BIOS Setup, BIOS will apply “10 SBE errors in one
hour” implementation. Enabling of this implementation and RAS features are mutually-exclusive
and automatically handled by system BIOS.
In non-RAS mode, BIOS maintains a counter for Single Bit ECC (SBE) errors. If ten SBE errors
occur within an hour, BIOS will disable SBE detection in the chipset to prevent the System
Event Log (SEL) from being filled up, and the OS from being halted.