Filter
Top Products
Intel® Server Board SE7520JR2 Table of Contents
Revision 1.0
C78844-002
v
3.2.2 PCI-X Hub (PXH)...................................................................................................33
3.2.2.1 Full-height Riser Slot..........................................................................................33
3.2.2.2 Low Profile Riser Slot.........................................................................................33
3.2.2.3 I/OxAPIC Controller............................................................................................ 34
3.2.2.4 SMBus Interface................................................................................................. 34
3.2.3 I/O Controller Hub (ICH5-R) ..................................................................................34
3.2.3.1 PCI Interface ......................................................................................................34
3.2.3.2 IDE Interface (Bus Master Capability and Synchronous DMA Mode)................ 34
3.2.3.3 SATA Controller .................................................................................................35
3.2.3.4 Low Pin Count (LPC) Interface ..........................................................................35
3.2.3.5 Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller) .35
3.2.3.6 Advanced Programmable Interrupt Controller (APIC)........................................ 36
3.2.3.7 Universal Serial Bus (USB) Controller ...............................................................36
3.2.3.8 RTC....................................................................................................................36
3.2.3.9 General Purpose I/O (GPIO)..............................................................................36
3.2.3.10 Enhanced Power Management........................................................................36
3.2.3.11 System Management Bus (SMBus 2.0) ........................................................... 36
3.3 Memory Sub-System .............................................................................................37
3.3.1 Memory Sizing ....................................................................................................... 37
3.3.2 Memory Population................................................................................................38
3.3.3 ECC Memory Initialization .....................................................................................40
3.3.4 Memory Test..........................................................................................................40
3.3.5 Memory Monitoring ................................................................................................ 41
3.3.6 Memory RASUM Features..................................................................................... 42
3.3.6.1 DRAM ECC – Intel® x4 Single Device Data Correction (x4 SDDC) .................42
3.3.6.2 Integrated Memory Scrub Engine ......................................................................42
3.3.6.3 Retry on Uncorrectable Error ............................................................................. 43
3.3.6.4 Integrated Memory Initialization Engine .............................................................43
3.3.6.5 DIMM Sparing Function .....................................................................................44
3.3.6.6 Memory Mirroring ............................................................................................... 45
3.3.6.7 Logging Memory RAS Information to the SEL ................................................... 47
3.4 I/O Sub-System .....................................................................................................47
3.4.1 PCI Subsystem ......................................................................................................47
3.4.1.1 P32-A: 32-bit, 33-MHz PCI Subsystem..............................................................48
3.4.1.2 P64-A and P64-B: 64-bit, 100MHz PCI Subsystem ........................................... 48
3.4.1.3 P64-Express: Dual x4 PCI Bus Segment...........................................................48
3.4.1.4 PCI Riser Slots...................................................................................................48
3.4.1.5 PCI Scan Order..................................................................................................49
3.4.1.6 PCI Bus Numbering ...........................................................................................49
3.4.1.7 Device Number and IDSEL Mapping ................................................................. 50
3.4.1.8 Resource Assignment ........................................................................................52
3.4.1.9 Automatic IRQ Assignment ................................................................................ 52
3.4.1.10 Option ROM Support........................................................................................ 52
3.4.1.11 PCI APIs........................................................................................................... 52
3.4.2 Split Option ROM...................................................................................................52