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Intel® Server Board SE7520JR2 Functional Architecture
Revision 1.0
C78844-002
75
3.5.1.4 System Management Mode Handling
The chipset supports System Management Mode (SMM) operation in one of three modes.
System Management RAM (SMRAM) provides code and data storage space for the SMI_L
handler code, and is made visible to the processor only on entry to SMM, or other conditions
that can be configured using Intel Lindenhurst PF chipset.
The MCH supports three SMM options:
• Compatible SMRAM (C_SMRAM)
• High Segment (HSEG)
• Top of Memory Segment (TSEG)
Three abbreviations are used later in the table that describes SMM Space Transaction
Handling.
SMM Space
Enabled
Transaction Address Space
(Adr)
DRAM Space (DRAM)
Compatible (C) A0000h to BFFFFh A0000h to BFFFFh
High (H) 0FEDA0000h TO 0FEDBFFFFh A0000h to BFFFFh
TSEG (T) (TOLM-TSEG_SZ) to TOLM (TOLM-TSEG_SZ) to
TOLM
Note: High SMM is different than in previous chipsets. In previous chipsets the high segment
was the 384KB region from A_0000h to F_FFFFh. However C_0000h to F_FFFFh was not
useful so it is deleted in MCH.
Note: TSEG SMM is different than in previous chipsets. In previous chipsets, the TSEG address
space was offset by 256MB to allow for simpler decoding and the TSEG was remapped to
directly under the TOLM. In the MCH, the TSEG region is not offset by 256MB and it is not
remapped.
Table 15: SMM Space Table
Global Enable
G_SMRAME
High Enable
H_SMRAME
TSEG Enable
TSEG_EN
Compatible
(C) Range
High (H)
Range
TSEG (T)
Range
0 X X Disable Disable Disable
1 0 0 Enable Disable Disable
1 0 1 Enable Disable Enable
1 1 0 Disable Enable Disable
1 1 1 Disable Enable Enable