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Connectors and Jumper Blocks Intel® Server Board SE7520JR2
Revision 1.0
C78844-002
184
Pin-Side
B
PCI Spec
Signal
Description Pin-Side
A
PCI Spec
Signal
Description
(2U)01=3x PCI
(2U)10=PXH 3 PCI-X-D
(2U)11=No Riser
1 Size 0=1U, 1 = 2U 1 PXH_PWR
OK
Input to indicate to PXH on active
riser that baseboard power is OK
7.3 System Management Headers
The baseboard provides several access points to the management buses built into the
baseboard. The following table provides the pinouts for each connector.
7.3.1 Intel® Management Module Connector
A 120-pin connector (J1C1) is included on the baseboard to support the optionally installed
“Professional” or “Advanced” Management modules.
Table 87: IMM Connector Pinout (J1C1)
FMC Signal Name FMC
Pin
Description
DVI_TX1M 2 Green TMDS differential DVI output of graphics chip
DVI_TX0M 3 Blue TMDS differential DVI output of graphics chip
DVI_TX1P 4 Green TMDS differential DVI output of graphics chip
DVI_TX0P 5 Blue TMDS differential DVI output of graphics chip
DVI_CLK_TX1CM 8 TMDS differential DVI clock output of graphics chip
DVI_TX2M 9 Red TMDS differential DVI output of graphics chip
DVI_CLK_TX1CP 10 TMDS differential DVI clock output of graphics chip
DVI_TX2P 11 Red TMDS differential DVI output of graphics chip
SIO_MS_DAT 14 KVM mouse data from SIO
SIO_KB_DAT 15 KVM keyboard data from SIO
SIO_MS_CLK 16 KVM mouse clock from SIO
SIO_KB_CLK 17 KVM keyboard clock from SIO
PS2_MS_DAT 18 KVM passthrough mouse data from PS2 connector
PS2_KB_DAT 19 KVM passthrough keyboard data from PS2 connector
PS2_MS_CLK 20 KVM passthrough mouse clock from PS2 connector
PS2_KB_CLK 21 KVM passthrough keyboard clock from PS2 connector
KM_INHIB_N 22 KVM enable of baseboard Switch for mouse and keyboard
FML_SDA 25 Fast Management Link Data In. This signal is driven by the FML Slave, i.e. NIC
controller
FML_MCL_I2CSCL 26 Fast Management Link Clock Out. This signal is driven by the FML Master, i.e.
FMM. When not configured as FML, this signal is used as I2C clock.