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User’s Manual 135
Table 9-8. Parallel Port D Register functions
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PDDR (R/W)
adr = 0x060
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
PDDCR (W)
adr = 0x066
out =
open
drain
out =
open
drain
out =
open
drain
out =
open
drain
out =
open
drain
out =
open
drain
out =
open
drain
out =
open
drain
PDFR (W)
adr = 0x065
xalt TXAxalt TXBxxxx
PDDDR (W)
adr = 0x067
dir =
out
dir =
out
dir =
out
dir =
out
dir =
out
dir =
out
dir =
out
dir =
out
PDB0R (W)
adr = 0x068
xxxxxxxPD0
PDB1R (W)
adr = 0x069
xxxxxxPD1x
PDB2R (W)
adr =0x 06A
xxxxxPD2xx
PDB3R (W)
adr = 0x06B
xxxxPD3xxx
PDB4R (W)
adr = 0x06C
xxxPD4xxxx
PDB5R (W)
adr = 0x06D
xxPD5xxxxx
PDB6R (W)
adr = 0x06E
xPD6xxxxxx
PDB7R (W)
adr = 0x06F
PD7xxxxxxx
Table 9-9. Parallel Port D Control Register (adr = 0x064)
Bits 7, 6 Bits 5, 4 Bits 3, 2 Bits 1, 0
x,x
00—clock upper nibble on pclk/2
01—clock on timer A1
10—clock on timer B1
11—clock on timer B2
x,x
00—clock lower nibble on pclk/2
01—clock on timer A1
10—clock on timer B1
11—clock on timer B2