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User’s Manual 299
B.1.12.2 Short Chip Select Timing
When short chip selects are enabled for read cycles, the chip select signals are active only
for the last part of the bus cycle. Wait states are inserted between T1 and T2, so this will
have no effect on the duration of the chip select signals in this mode. The timing diagrams
below illustrate the actual timing for the different divided cases. In these cases the chip
selects are two clock cycles (of the fast oscillator) long.
Figure B-3. Short Chip Select Timing: CLK/8, Read Operation
oscillator
ADDR
DATA
T1 T2
Valid
/OEx
/CSx
clock
divide-b
y
-8 mode