Filter
Top Products
322 Rabbit 3000 Microprocessor
C.3.1 Peripheral Interrupt Prioritization
Most interrupts can be programmed to occur at any of three priority levels, but several are
restricted to Level 3 (the highest priority) only. The interrupts restricted to Level 3 are sys-
tem mode violation, stack limit violation, write protection violation, and the secondary
watchdog. In addition, any interrupt assigned to User mode is prevented (by hardware)
from requesting a Level 3 interrupt. If a user-assigned interrupt is programmed to occur at
Level 3, the hardware will automatically modify the request to occur at Level 2. Within a
given interrupt priority level, the interrupts are prioritized according to Table C-5.