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314 Rabbit 3000 Microprocessor
B.1.14 Quadrature Decoder Improvements
The quadrature decoder counters can now be expanded to 10 bits instead of 8 bits. This is
controlled by bit 5 in QDCR, listed in Table B-28. The additional two bits can be read in
the QDCxHR registers, listed in Table B-29.
NOTE: Bit 5 of QDCR was always written with a zero in the original Rabbit 3000 chip.
Table B-28. Quadrature Decoder Control Register
Quadrature Decoder Control Register (QDCR) (Address = 0x0091)
Bit(s) Value Description
7:6 00
Disable Quadrature Decoder 2 inputs. Writing a new value to these bits will not
cause Quadrature Decoder 2 to increment or decrement.
01 This bit combination is reserved and should not be used.
10 Quadrature Decoder 2 inputs from Port F bits 3 and 2.
11 Quadrature Decoder 2 inputs from Port F bits 7 and 6.
5 0 Eight bit quadrature decoder counters.
1 Ten bit quadrature decoder counters.
4 This bit is reserved and should be written as zero.
3:2 00
Disable Quadrature Decoder 1 inputs. Writing a new value to these bits will not
cause Quadrature Decoder 1 to increment or decrement.
01 This bit combination is reserved and should not be used.
10 Quadrature Decoder 1 inputs from Port F bits 1 and 0.
11 Quadrature Decoder 1 inputs from Port F bits 5 and 4.
1:0 00 Quadrature Decoder interrupts are disabled.
01 Quadrature Decoder interrupt use Interrupt Priority 1.
10 Quadrature Decoder interrupt use Interrupt Priority 2.
11 Quadrature Decoder interrupt use Interrupt Priority 3.
Table B-29. Quadrature Decoder Count High Register
Quadrature Decoder Count High Register (QDC1HR) (Address = 0x0095)
(QDC2HR) (Address = 0x0097)
Bit(s) Value Description
7:2 read These bits are reserved and will always read as zeros.
1:0 read The current value of bits 9-8 of the Quadrature Decoder counter is reported.