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User’s Manual 139
Table 9-11. Parallel Port E Register functions
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PEDR (R/W)
adr = 0x070
PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
PEFR (W)
adr = 0x075
alt /I7 alt /I6 alt /I5 alt /I4 alt /I3 alt /I2 alt /I1 alt /I0
PEDDR (W)
adr = 0x077
dir =
out
dir =
out
dir =
out
dir =
out
dir =
out
dir =
out
dir =
out
dir =
out
PEB0R (W)
adr = 0x078
xxxxxxxPE0
PEB1R (W)
adr = 0x079
xxxxxxPE1x
PEB2R (W)
adr = 0x07A
xxxxxPE2xx
PEB3R (W)
adr = 0x07B
xxxxPE3xxx
PEB4R (W)
adr = 0x07C
xxxPE4xxxx
PEB5R (W)
adr = 0x07D
xxPE5xxxxx
PEB6R (W)
adr = 0x07E
xPE6xxxxxx
PEB7R (W)
adr = 0x07F
PE7xxxxxxx
Table 9-12. Parallel Port E Control Register (adr = 0x074)
Bits 7, 6 Bits 5, 4 Bits 3, 2 Bits 1, 0
x,x
00—clock upper nibble on pclk/2
01—clock on timer A1
10—clock on timer B1
11—clock on timer B2
x,x
00—clock lower nibble on pclk/2
01—clock on timer A1
10—clock on timer B1
11—clock on timer B2