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Functional Description for the MSP50C614
1-6
The core processor is a general-purpose 16 bit micro-controller with DSP
capability. The basic core block includes a computational unit (CU), data
address unit, program address unit, two timers, eight level interrupt processor,
and several system and control registers. The core processor provides
break-point capability to the MSP50C6xx code development software
(EMUC6xx).
The processor is a Harvard type for efficient DSP algorithm execution. It re-
quires separate program and data memory blocks to permit simultaneous ac-
cess. The ROM has a protection scheme to prevent third-party pirating. It is
configured in 32K 17-bit words.
The total ROM space is divided into two areas: 1) The lower 2K words are re-
served by Texas Instruments for a built-in self-test, 2) the upper 30K is for user
program/data.
The data memory is internal static RAM. The RAM is configured in 640 17-bit
words. Both memories are designed to consume minimum power at a given
system clock and algorithm acquisition frequency.
A flexible clock generation system is included that enables the software to
control the clock over a wide frequency range. The implementation uses a
phase-locked loop (PLL) circuit to generate the processor clock. The
Processor clock is programmable in 65.536-kHz steps between 64 kHz and
12.32 MHz. The PLL reference clock is also selectable; either a
resistor-trimmed oscillator or a crystal-referenced oscillator may be used.
Internal and peripheral clock sources are controlled separately to provide
different levels of power management (see Figure 1–2).