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User Manual November 21
88 Chapter 7: Device Configuration
Each HyperTransport link can be enabled separately. Each link can be 8- or 16-bits wide.
Only the 940-pin AMD Opteron processor can have three links; a 754-pin AMD Athlon
64 has one HyperTransport port.
Figure 7-19: Northbridge DDR2 Training Properties Dialog
When the DDR2 DRAM Controller is selected and DDR2 DRAM is being used you can
manually modify these values to verify the correctness of the DDR2 training algorithmn.
The DDR2 Training Properties Dialog contains the lowest and highest values that the
BIOS can program into these registers. While these registers are programmed out of
bounds DRAM access will be corrupted.
Note the DDR2 Training Properties Dialog is only useful for BIOS developer and the
values should only be modified and used by BIOS developers.
If Log PCI Configuration Cycles is selected, the device produces log messages whenever
the PCI configuration data register (0xCFC) is accessed. Log files can get very large.
Reads from this I/O-mapped register produce PCI CONFIG READ messages, and writes
to the register produce PCI CONFIG WRITE messages. The formats of the PCI CONFIG
READ and PCI CONFIG WRITE messages are as follows:
PCI CONFIG READ Bus a, Device b, Function c, Register d, Data e
PCI CONFIG WRITE Bus a, Device b, Function c, Register d, Data e
where a, b, c, d, and e are all hexadecimal numbers.