AMD 4.4.5 Switch User Manual

AMD Confidential
User Manual November 21
, 2008
Chapter 7: Device Configuration 115
APIC initialization information.
<INSTR Device="CPU0" Type="FJMP" ICount="6778" JMP="1" RIP="f86b0619" />
An FJMP Instruction. RIP is optional and is only used to double check whether if the
FJMP is taken at the correct instruction. JMP attribute can have the following values:
JMP=0: Force Do-not-take-jump for this instruction
JMP=1: Force Take-jump for this instruction
<Event Device="CPU0" Type="IOW" ICount="6817" Address="a038" Size="2">
<Data Length="2" Value="40af" />
Defines an IOR or IOW dormant event.
<Event Device="CPU0" Type="DMAW" ICount="8403" Address="000000000c254340"
<Data Length="64"
002fc2460067c2460085c24600a3c24600909090909090909090909090" />
Defines a DMAW event.
<Event Device="CPU0" Type="PIN" ICount="325496" Name="INTR" Level="A" />
Defines an INTR PIN event. Level="A" for Asserted or "D" for Deasserted. Name could
be INTR, RESET, A20M, NMI, PAUSE, SMI, and <Unknown>.
<Event Device="TO_DO_IN_NB" Type="APIC" ICount="325496" Name="EXTINT"
DestinationMode="F" DeliveryMode="07" Level="F" TriggerMode="F" Vector="00"
Destination="00" />
Defines an APIC Event. Name could be EOI, INIT, STARTUP, SMI, NMI, INTR,
REMOTE READ, EXTINT, LPARB, and Unknown. Device can be the name of the
device that issues the interrupt. Current XTR implementation ignores the name of the
<Event Device="CPU0" Type="INTACK" ICount="325496" Vector="00000000000000d1" />
Defines an INTACK cycle event.
<Event Device="XTR" Type="EOT" ICount="400001" />
Defines an End of Trace (EOT) event.
<Event Device="CPU0" Type="RDMSR" ICount="1404861740" Address="00000010"
Data="0000000053BC7D2C" />
Defines a RDMSR event.
<Event Device="CPU0" Type="MEMR" ICount="3133971257"
Address="00000000000A88B2" Size="1">
<Data Length="1" Value="FF" />