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User Manual November 21
Chapter 7: Device Configuration 55
7.1 AweSim Processor Device
The AweSim processor device provides a simulation of an AMD microprocessor.
Three interfaces are used in the AweSim device:
CPU Bus 0. This interface is used to issue memory and I/O read and write requests, as
well as cache control and input/output signal messages. This interface is generally
connected to the Northbridge device.
Interrupt Bus. This interface is used to communicate interrupt request and acknowledge
messages. This interface is connected to whichever device is used to generate and control
interrupts - typically the Southbridge device.
System Messages Interface. This interface is used by the processor device to output
ASCII and binary log information.
Initialization and Reset State
The processor device's state at initialization is equivalent to an industry-standard x86
processor at initialization. The L1 cache and APIC interfaces are disabled, the debugger
is off, and the L1 cache is configured as two 2-way, 512-line, and 64-byte caches.
When the processor device receives a reset, the device resets its internal state in a manner
consistent with a standard x86 processor. No configuration information is modified.
Contents of a BSD
The BSD file contains the current state of all internal processor registers, state variables,
etc. It also contains all configuration information. Any memory configured locally to the
processor is saved in the BSD.
The Device Properties Window is used to set various processor identification and
behavior options. Figure 7-1 shows the Processor Type tab for the AweSim processor
device. Here you can specify which member of the AMD microprocessor family should
be simulated. The default is a standard AMD microprocessor. See Section A.2.3, Product
Files (*.ID), on page 179.
Note: The public release version of the simulator doesn't contain any product files!