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12 www.xilinx.com ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
Chapter 1: Introduction
R
The ML361 demonstrates a 64-/72-bit interface to a 128 MByte, 200 MHz DDR SDRAM
DIMM, a 72-bit interface to five 256 Mbit, 200 MHz DDR SDRAM components, and an
additional 8-bit interface to a 256 Mbit, 200 MHz DDR SDRAM component on one of the
top banks.
Features
The key features of the ML361 are summarized below:
• One Virtex-II Pro FPGA (XC2VP20FF1152-6)
• One DDR SDRAM DIMM (MT4VDDT1664-AG-40BC3)
♦ 128 MBytes
♦ 64-/72-bit data interface
• Five DDR SDRAMs (four MT46V16M16TG-5B devices and one MT46V32M8TG-5B
device)
♦ 1.28 Gbits
♦ 72-bit data interface
• One DDR SDRAM (MT46V32M8TG-5B)
♦ 256 Mbits
♦ 8-bit data interface
• Two separate controllers for each 72-bit memory interface
• 200 MHz interface
• The memory interfaces are located on the FPGA left/right interface and top I/O
banks (banks 1, 2, 3, 6, and 7)