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ML361 Virtex-II Pro Memory Board www.xilinx.com 25
UG060 (v1.2) November 8, 2007
R
Chapter 4
Signal Integrity Recommendations and
Simulations
This chapter provides the following information:
• Summary of the termination schemes for various signals (“Termination and
Transmission Line Summaries,” page 25)
• Summary of the observed duty cycles for all signals in the IBIS simulations (“Duty
Cycle Summary,” page 27)
• IBIS simulations and duty cycle measurements (“IBIS Simulations,” page 29)
Termination and Transmission Line Summaries
Table 4-1 summarizes the terminations for the five DDR SDRAM components at the FPGA
and at memory.
Table 4-2 summarizes the terminations for the DIMM at the FPGA and at memory.
Table 4-1: DDR SDRAM Terminations
No. Signal
Drivers at the
FPGA
Termination at FPGA Termination at Memory
1 Data (DQ) SSTL2_C2 50Ω pull up to 1.3 V 50Ω pull-up to 1.3 V
2 Data Strobe (DQS) SSTL2_C2 50Ω pull up to 1.3 V 50Ω pull-up to 1.3 V
3 Data Mask (DM) SSTL2_C2 50Ω pull up to 1.3 V 50Ω pull-up to 1.3 V
4 Clock (CK, CKn) SSTL2_C2 50Ω pull up to 1.3 V 50Ω pull-up to 1.3 V
5 Address (A, BA) SSTL2_C2 No termination 50Ω pull-up to 1.3 V after the
last component
6 Control (RASn, CASn, WEn,
CSn, CKE)
SSTL2_C2 No termination 50Ω pull-up to 1.3 V after the
last component
Table 4-2: DIMM Terminations
No. Signal
Drivers at the
FPGA
Termination at FPGA Termination at Memory
1 Data (DQ) SSTL2_C2 50Ω pull-up to 1.3 V 50Ω pull-up to 1.3 V
2 Data Strobe (DQS) SSTL2_C2 50Ω pull-up to 1.3 V 50Ω pull-up to 1.3 V
3 Data Mask (DM) SSTL2_C2 50Ω pull-up to 1.3 V 50Ω pull-up to 1.3 V