Filter
Top Products
ML361 Virtex-II Pro Memory Board www.xilinx.com 47
UG060 (v1.2) November 8, 2007
IBIS Simulations
R
Typical Case Simulation at First DDR Component
For the typical case simulation at the first DDR component, the resulting duty cycle is
48.94/51.2. Figure 4-17 shows the simulation screen capture for this case.
X-Ref Target - Figure 4-17
Figure 4-17: Address/Control Signals at First DDR Memory (Typical Case)
ug060_c5_17_091003