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ML361 Virtex-II Pro Memory Board www.xilinx.com 61
UG060 (v1.2) November 8, 2007
IBIS Simulations
R
Clock Signals with 55Ω Transmission Line Impedance
For the typical case simulation with a 55Ω transmission line impedance, the resulting duty
cycle is 48.1/51.48. Figure 4-31 shows the simulation screen capture for this case.
X-Ref Target - Figure 4-31
Figure 4-31: Clock Signals with 55Ω Impedance
ug060_c5_31_091003