Xilinx ML361 Virtex-II Pro Computer Hardware User Manual


  Open as PDF
of 90
 
ML361 Virtex-II Pro Memory Board www.xilinx.com 41
UG060 (v1.2) November 8, 2007
IBIS Simulations
R
Typical Case for Clock Signals
For the typical case simulation, the resulting duty cycle is 48.1/52.04. Figure 4-11 shows the
simulation screen capture for this case.
X-Ref Target - Figure 4-11
Figure 4-11: Clock Signal from FPGA to Memory (Typical Case)
ug060_c5_12_091003
 previous next