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26 www.xilinx.com ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
Chapter 4: Signal Integrity Recommendations and Simulations
R
Terminations and Transmission Lines for DDR Components
Data and Clock Signals (DQ, DQS, DM, CLK)
For these DDR signals, the terminations at the FPGA and memory consist of a 50Ω parallel
termination pulled up to 1.3 V.
Use 50
Ω transmission lines with less than ± 1% tolerance on the transmission line
impedance. The recommendations for the transmission line lengths are as follows:
• All these data and clock signals are point-to-point from the FPGA to each DDR
component. All signals going to one individual DDR SDRAM component need to be
matched with respect to each other with a ± 2% tolerance.
• All signals going to the first component are matched to a trace length of 2.8 inches
with a ± 2% tolerance. The 2.5 inch requirement includes the FPGA internal package
skew (available on the pinout table) and the skew between the ball of the FPGA to the
resistor pack as well as the length of the actual trace.
• The trace length variation on these signals across the five DDR components is kept as
small as possible to enable data capture while also ensuring they fall within the
address window. The trace lengths on all five DDR components are: 2.8 inches, 2.8
inches, 3.5 inches, 3.8 inches, and 3.8 inches. All signals corresponding to the same
DDR component are matched as close as ± 1% of the above mentioned trace lengths.
Microstrip is used to model the transmission lines in the IBIS simulations.
Address and Control Signals (A, BA, RASn, CASn, WEn, CSn, CKE)
For the address and control signals, no termination is required at the FPGA. At memory, a
50
Ω resistor pulled up to 1.3 V at the end of the daisy chain is required (after the last DDR
component).
Use 50
Ω transmission lines with ± 5% tolerance from the FPGA to all the memory
components. The recommendations for the transmission line lengths are as follows:
• All the signals are routed in a daisy chain fashion.
• There is a maximum of 2.5 inch trace with ± 2% tolerance from the FPGA to the first
DDR component. The 2.5 inch requirement includes the FPGA internal package skew
(that is available on the pinout table) and the skew between the ball of the FPGA to
the resistor pack as well as the length of the actual trace.
• 0.6 inches of distance with ± 2% tolerance is used in the trace length calculations
below between the individual components. Ideally, straight line routing is desired.
During placement, the components are placed as close as 0.5 inches or lesser by
straight line routing, if possible. The main requirement is that all signals going to each
DDR component must be matched by ± 2% tolerance.
4 3 pairs of Clocks (CK, CKn) SSTL2_C2 50Ω pull-up to 1.3 V 50Ω pull-up to 1.3 V
5 Address (A, BA) SSTL2_C2_DCI No termination No termination
6 Control (RASn, CASn, WEn,
CSn, CKE and others)
SSTL2_C2_DCI No termination No termination
Table 4-2: DIMM Terminations
No. Signal
Drivers at the
FPGA
Termination at FPGA Termination at Memory