Xilinx ML361 Virtex-II Pro Computer Hardware User Manual


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ML361 Virtex-II Pro Memory Board www.xilinx.com 35
UG060 (v1.2) November 8, 2007
IBIS Simulations
R
Eye Diagram
Figure 4-5 shows the eye diagram for the data signals from the FPGA to the last memory
component.
X-Ref Target - Figure 4-5
Figure 4-5: Eye Diagram for Data from the FPGA to Last Memory Component
ug060_c5_05_091003
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