Xilinx ML361 Virtex-II Pro Computer Hardware User Manual


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ML361 Virtex-II Pro Memory Board www.xilinx.com 33
UG060 (v1.2) November 8, 2007
IBIS Simulations
R
Slow Weak Corner Case for Data from the FPGA to the Last DDR Component
For the slow weak case simulation, the resulting duty cycle is 47.52/52.06. Figure 4-3
shows the simulation screen capture for this case.
X-Ref Target - Figure 4-3
Figure 4-3: Data Signal from FPGA to Memory (Slow Weak Case)
ug060_c5_03_091003
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