Xilinx ML361 Virtex-II Pro Computer Hardware User Manual


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6 www.xilinx.com ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
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Figure 4-29: Data Signals from Memory to FPGA (55Ω Impedance) . . . . . . . . . . . . . . . . . 59
Figure 4-30: Clock Signals with 45Ω Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 4-31: Clock Signals with 55Ω Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 4-32: Address/Control Signals with 45Ω Impedance Measured at First DDR
Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 4-33: Address/Control Signals with 55Ω Impedance Measured at First DDR
Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Chapter 5: Board Layout Guidelines
Appendix A: Related Documentation
Appendix B: FPGA Pinout
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