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24 www.xilinx.com ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
Chapter 3: Electrical Requirements
R
Table 3-7: Input/Output Power
Name
Frequency
(MHz)
I/O Standard
Type
Total
Number
of Inputs
Total
Number
of
Outputs
Average
IOB
Toggle
Rate
%
Average
Output
Enable
Rate
%
Average
Output
Load
(pF)
IOB
Registers
VCC
INT
Subtotal
(mW)
VCCO
Subtotal
(mW)
Jpheader 200 LVCMOS25_12 0 16 25% 100% 0 SDR 2 30
ddr_dq 200 SSTL2_II 138 138 80% 50% 5 DDR 462 877
ddr_dqs 2000 SSTL2_II 18 18 80% 50% 5 DDR 335 363
ddr_address 200 SSTL2_II 0 15 25% 100% 3 SDR 1 106
ddr_control 200 SSTL2_II 0 5 25% 100% 3 SDR 0 35
dimm_address 200 SSTL2_I_DCI 0 15 25% 100% 12 SDR 13 157
dimm_control 200 SSTL2_I_DCI 0 4 50% 100% 12 SDR 12 96
ddr_clks 200 SSTL2_II 0 2 100% 100% 3 DDR 0 42
Display 200 LVCMOS25_12 0 14 6% 100% 0 SDR 1 6
dimm_control_1 200 SSTL2_II 0 3 50% 100% 12 SDR 0 28
ddr_dm 200 SSTL2_II 0 17 10% 100% 5 SDR 2 100
dimm_clks 200 SSTL2_II 0 6 100% 100% 12 SDR 1 82
top_dq 200 SSTL2_II_DCI 8 8 80% 50% 5 DDR 39 366
top_dqs 200 SSTL2_II_DCI 1 1 80% 50% 5 DDR 15 103
top_address 200 SSTL2_I_DCI 0 15 25% 100% 5 SDR 13 153
top_control 200 SSTL2_I_DCI 0 5 25% 100% 5 SDR 12 95
Total 910 2645