Xilinx ML361 Virtex-II Pro Computer Hardware User Manual


  Open as PDF
of 90
 
50 www.xilinx.com ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
Chapter 4: Signal Integrity Recommendations and Simulations
R
Typical Case Simulation at Last DDR Component
For the typical case simulation at the last DDR component, the resulting duty cycle is
49.22/50.92. Figure 4-20 shows the simulation screen capture for this case.
X-Ref Target - Figure 4-20
Figure 4-20: Address/Control Signals at Last DDR Memory (Typical Case)
ug060_c5_20_091003
 previous next