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ML361 Virtex-II Pro Memory Board www.xilinx.com 29
UG060 (v1.2) November 8, 2007
IBIS Simulations
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IBIS Simulations
This section summarizes various simulations run on the Memory Board using IBIS. It
defines the test conditions and provides color-coded screen captures of the results. The
resulting signal duty cycles are given also.
The simulations have been divided into the following categories:
1. Data Signal Simulations
a. Data Signals from the FPGA to the Last Memory Component
- Typical Case
- Slow Weak Case
- Fast Strong Case
- Eye Diagram
b. Data Signals from the Last Memory Component to the FPGA
- Typical Case
- Slow Weak Case
- Fast Strong Case
- Eye Diagram
2. Clock Signal Simulations
a. Clock Signals from the FPGA to the Last Memory Component
- Typical Case
- Slow Weak Case
- Fast Strong Case
- Eye Diagram
3. Address and Control Signal Simulations
a. Address and Control Signals from the FPGA to the First/Last/Middle Memory
Component
- All Memory Components (Typical Case)
- First DDR Component (Typical, Slow Weak, Fast Strong Cases)
- Last DDR Component (Typical, Fast Strong, Slow Weak Cases)
- Middle DDR Component (Typical, Slow Weak, Fast Strong Cases)
4. Typical Case Simulations with 10% Tolerance for:
a. Data Signals
- Data Signals from the Last DDR Memory to the FPGA with 45
Ω Transmission
Lines (Typical)
- Data Signals from the Last DDR Memory to the FPGA with 55
Ω Transmission
Lines (Typical)
- Data Signals from the FPGA to the Last DDR Memory with 45
Ω Transmission
Lines (Typical)
- Data Signals from Memory to the FPGA with 55
Ω transmission lines (Typical)
b. Clock Signals
- Clock Signals with 45
Ω Transmission Lines (Typical)
- Clock Signals with 55
Ω Transmission Lines (Typical)