Xilinx ML361 Virtex-II Pro Computer Hardware User Manual


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ML361 Virtex-II Pro Memory Board www.xilinx.com 59
UG060 (v1.2) November 8, 2007
IBIS Simulations
R
Data Signals from Memory to the FPGA with 55Ω Transmission Line Impedance
For the typical case simulation from memory to the FPGA, the resulting duty cycle is
48.66/51.48. Figure 4-29 shows the simulation screen capture for this case.
X-Ref Target - Figure 4-29
Figure 4-29: Data Signals from Memory to FPGA (55Ω Impedance)
ug060_c5_29_091003
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