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ML361 Virtex-II Pro Memory Board www.xilinx.com 43
UG060 (v1.2) November 8, 2007
IBIS Simulations
R
Fast Strong Case for Clock Signals
For the fast strong case simulation, the resulting duty cycle is 48.1/51.48. Figure 4-13
shows the simulation screen capture for this case.
X-Ref Target - Figure 4-13
Figure 4-13: Clock Signal from FPGA to Memory (Fast Strong Case)
ug060_c5_11_091003