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ML361 Virtex-II Pro Memory Board www.xilinx.com 63
UG060 (v1.2) November 8, 2007
IBIS Simulations
R
Address and Control Signals with 55Ω Transmission Lines Measured at the First
DDR Component
For the typical case simulation with a 55Ω transmission line impedance measured at the
first DDR component, the resulting duty cycle is 48.66/51.48. Figure 4-33 shows the
simulation screen capture for this case.
X-Ref Target - Figure 4-33
Figure 4-33: Address/Control Signals with 55Ω Impedance Measured at First DDR
Component
ug060_c5_33_091003