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46 www.xilinx.com ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
Chapter 4: Signal Integrity Recommendations and Simulations
R
Typical Case Simulation at All Memory Components
Figure 4-16 shows the simulation screen capture for the typical case for all memory
components.
X-Ref Target - Figure 4-16
Figure 4-16: Address/Control Signals for All Memories
ug060_c5_16_091003