Filter
Top Products
40 www.xilinx.com ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
Chapter 4: Signal Integrity Recommendations and Simulations
R
Clock Signal Simulations
The simulations in this subsection test the unidirectional clock signals from the FPGA to
memory. Simulations were performed for the following cases: typical, slow weak, and fast
strong. An eye diagram is provided also.
All clock signal simulations below have the following test conditions for typical, slow
weak, and fast strong cases:
• Topology for clock signals: 50
Ω transmission lines
• At memory (yellow signal): 50
Ω parallel termination pulled up to 1.3 V
• At FPGA (red signal): 50
Ω parallel termination pulled up to 1.3 V (SSTL2C2 drivers at
FPGA).
Figure 4-10 shows the clock signal terminations.
X-Ref Target - Figure 4-10
Figure 4-10: Clock Signal Terminations
ug060_c5_10_091003