Xilinx ML361 Virtex-II Pro Computer Hardware User Manual


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ML361 Virtex-II Pro Memory Board www.xilinx.com 5
UG060 (v1.2) November 8, 2007
Chapter 1: Introduction
Figure 1-1: Simplified Block Diagram of Memory Board Interfaces . . . . . . . . . . . . . . . . . 11
Chapter 2: Architecture
Figure 2-1: ML361 Board Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 3: Electrical Requirements
Chapter 4: Signal Integrity Recommendations and Simulations
Figure 4-1: Data Signal Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 4-2: Data Signal from FPGA to Memory (Typical Case) . . . . . . . . . . . . . . . . . . . . . 32
Figure 4-3: Data Signal from FPGA to Memory (Slow Weak Case). . . . . . . . . . . . . . . . . . 33
Figure 4-4: Data Signal from FPGA to Memory (Fast Strong Case). . . . . . . . . . . . . . . . . . 34
Figure 4-5: Eye Diagram for Data from the FPGA to Last Memory Component. . . . . . . 35
Figure 4-6: Data Signal from Last Memory at FPGA (Typical Case) . . . . . . . . . . . . . . . . . 36
Figure 4-7: Data Signal from Last Memory at FPGA (Slow Weak Corner Case). . . . . . . 37
Figure 4-8: Data Signal from Memory at FPGA (Fast Strong Corner Case) . . . . . . . . . . . 38
Figure 4-9: Eye Diagram for Data at the FPGA to the Last Memory Component . . . . . . 39
Figure 4-10: Clock Signal Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 4-11: Clock Signal from FPGA to Memory (Typical Case) . . . . . . . . . . . . . . . . . . . 41
Figure 4-12: Clock Signal from FPGA to Memory (Slow Weak Case). . . . . . . . . . . . . . . . 42
Figure 4-13: Clock Signal from FPGA to Memory (Fast Strong Case) . . . . . . . . . . . . . . . . 43
Figure 4-14: Eye Diagram for Clock at Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 4-15: Address and Control Signal Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 4-16: Address/Control Signals for All Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 4-17: Address/Control Signals at First DDR Memory (Typical Case). . . . . . . . . . 47
Figure 4-18: Address/Control Signals at First DDR Memory (Slow Weak Case) . . . . . . 48
Figure 4-19: Address/Control Signals at First DDR Memory (Fast Strong Case) . . . . . . 49
Figure 4-20: Address/Control Signals at Last DDR Memory (Typical Case) . . . . . . . . . . 50
Figure 4-21: Address/Control Signals at Last DDR Memory (Slow Weak Case). . . . . . . 51
Figure 4-22: Address/Control Signals at Last DDR Memory (Fast Strong Corner Case) 52
Figure 4-23: Address/Control Signals at Middle DDR Memory (Typical Case) . . . . . . . 53
Figure 4-24: Address/Control Signals at Middle DDR Memory (Slow Weak Corner
Case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 4-25: Address/Control Signals at Middle DDR Memory (Fast Strong Corner
Case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 4-26: Data Signals from Last DDR Memory to FPGA (45Ω Impedance) . . . . . . . 56
Figure 4-27: Data Signals from Last DDR Memory to FPGA (55Ω Impedance) . . . . . . . 57
Figure 4-28: Data Signals from FPGA to Last DDR Memory (45Ω Impedance) . . . . . . . 58
Schedule of Figures
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