Xilinx ML361 Virtex-II Pro Computer Hardware User Manual


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34 www.xilinx.com ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
Chapter 4: Signal Integrity Recommendations and Simulations
R
Fast Strong Case for Data Signals from the FPGA to the Last DDR Component
For the fast strong case simulation, the resulting duty cycle is 46.4/52.9. Figure 4-4 shows
the simulation screen capture for this case.
X-Ref Target - Figure 4-4
Figure 4-4: Data Signal from FPGA to Memory (Fast Strong Case)
ug060_c5_04_091003
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