Xilinx ML361 Virtex-II Pro Computer Hardware User Manual


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38 www.xilinx.com ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
Chapter 4: Signal Integrity Recommendations and Simulations
R
Fast Strong Corner Case for Data from Memory to the FPGA
For the fast strong case simulation, the resulting duty cycle is 48.38/51.76. Figure 4-8
shows the simulation screen capture for this case.
X-Ref Target - Figure 4-8
Figure 4-8: Data Signal from Memory at FPGA (Fast Strong Corner Case)
ug060_c5_08_031204
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