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56 www.xilinx.com ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
Chapter 4: Signal Integrity Recommendations and Simulations
R
Simulations with 10% Tolerance on the Transmission Line Impedance
These simulations illustrate the typical cases for data, clock, and address and control
signals.
Data Signals
This subsection provides the data simulation results for the following typical cases:
• From the last DDR memory to the FPGA (45
Ω transmission line impedance)
• From the last DDR memory to the FPGA (55
Ω transmission line impedance)
• From the FPGA to the last DDR memory (45
Ω transmission line impedance)
• From the memory to the FPGA (55
Ω transmission line impedance)
Data Signals from the Last DDR Memory to the FPGA with 45Ω Transmission Line
Impedance
For the typical case simulation from the last DDR component to the FPGA, the resulting
duty cycle is 48.66/51.48. Figure 4-26 shows the simulation screen capture for this case.
X-Ref Target - Figure 4-26
Figure 4-26: Data Signals from Last DDR Memory to FPGA (45Ω Impedance)
ug060_c5_26_031204