Filter
Top Products
ML361 Virtex-II Pro Memory Board www.xilinx.com 45
UG060 (v1.2) November 8, 2007
IBIS Simulations
R
Address and Control Signal Simulations
The simulations in this subsection test the unidirectional address and control signals from
the FPGA to five DDR memory components. Simulations were performed on the first,
middle, and last DDR memory component for the following cases: typical, slow weak, and
fast strong.
All clock signal simulations below have the following test conditions for typical, slow
weak, and fast strong cases:
• Topology: The FPGA and the five DDR components are placed in a straight line in a
daisy chain configuration.
♦ The distance between the FPGA and the first DDR component – 2.1 inches
♦ The distance between adjacent DDR components – 0.7 inches
♦ The distance between the FPGA and the last DDR component – 4.8 inches
• At memory (yellow signal): 50
Ω resistor pulled up to 1.3 V after the last DDR SDRAM
component.
• At FPGA (red signal): 50
Ω transmission line is used (SSTL2C2 drivers at the FPGA).
Figure 4-15 shows the address and control signal terminations.
X-Ref Target - Figure 4-15
Figure 4-15: Address and Control Signal Terminations
ug060_c5_15_091003