Filter
Top Products
36 www.xilinx.com ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
Chapter 4: Signal Integrity Recommendations and Simulations
R
Data Signals from the Last Memory to the FPGA: Measured at FPGA
The simulations in this subsection test the data signals from the last memory to the FPGA.
Simulations were performed for the following cases: typical, slow weak, and fast strong.
An eye diagram is provided also.
Typical Case for Data from the Last DDR Memory Device to the FPGA
For the typical case simulation, the resulting duty cycle is 48.64/51.78. Figure 4-6 shows
the simulation screen capture for this case.
X-Ref Target - Figure 4-6
Figure 4-6: Data Signal from Last Memory at FPGA (Typical Case)
ug060_c5_06_031204