Xilinx ML361 Virtex-II Pro Computer Hardware User Manual


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ML361 Virtex-II Pro Memory Board www.xilinx.com 37
UG060 (v1.2) November 8, 2007
IBIS Simulations
R
Slow Weak Corner Case for Data Signals from the Last DDR Memory to the FPGA
For the slow weak case simulation, the resulting duty cycle is 49.52/50.64. Figure 4-7
shows the simulation screen capture for this case.
X-Ref Target - Figure 4-7
Figure 4-7: Data Signal from Last Memory at FPGA (Slow Weak Corner Case)
u
g
060_c5_07_031204
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