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60 www.xilinx.com ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
Chapter 4: Signal Integrity Recommendations and Simulations
R
Clock Signals
This subsection provides the clock simulation results for the following typical cases:
• With 45
Ω transmission line impedance
• With 55
Ω transmission line impedance
Clock Signals with 45Ω Transmission Line Impedance
For the typical case simulation with a 45Ω transmission line impedance, the resulting duty
cycle is 48.66/ 52.04. Figure 4-30 shows the simulation screen capture for this case.
X-Ref Target - Figure 4-30
Figure 4-30: Clock Signals with 45Ω Impedance
ug060_c5_30_091003