Xilinx ML361 Virtex-II Pro Computer Hardware User Manual


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ML361 Virtex-II Pro Memory Board www.xilinx.com 51
UG060 (v1.2) November 8, 2007
IBIS Simulations
R
Slow Weak Case Simulation at Last DDR Component
For the slow weak case simulation at the last DDR component, the resulting duty cycle is
49.22/50.63. Figure 4-21 shows the simulation screen capture for this case.
X-Ref Target - Figure 4-21
Figure 4-21: Address/Control Signals at Last DDR Memory (Slow Weak Case)
ug060_c5_22_091003
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