Xilinx ML361 Virtex-II Pro Computer Hardware User Manual


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ML361 Virtex-II Pro Memory Board www.xilinx.com 53
UG060 (v1.2) November 8, 2007
IBIS Simulations
R
Typical Case Simulation at Middle DDR Component
For the typical case simulation at the middle DDR component, the resulting duty cycle is
49.23/51.49. Figure 4-23 shows the simulation screen capture for this case.
X-Ref Target - Figure 4-23
Figure 4-23: Address/Control Signals at Middle DDR Memory (Typical Case)
ug060_c5_23_091003
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