Xilinx ML361 Virtex-II Pro Computer Hardware User Manual


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54 www.xilinx.com ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
Chapter 4: Signal Integrity Recommendations and Simulations
R
Slow Weak Corner Case Simulation at Middle DDR Component
For the slow weak corner case simulation at the middle DDR component, the resulting
duty cycle is 49.22/50.64. Figure 4-24 shows the simulation screen capture for this case.
X-Ref Target - Figure 4-24
Figure 4-24: Address/Control Signals at Middle DDR Memory (Slow Weak Corner
Case)
ug060_c5_24_091003
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