Xilinx ML361 Virtex-II Pro Computer Hardware User Manual


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42 www.xilinx.com ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
Chapter 4: Signal Integrity Recommendations and Simulations
R
Slow Weak Case for Clock Signals
For the slow weak case simulation, the resulting duty cycle is 48.66/51.48. Figure 4-12
shows the simulation screen capture for this case.
X-Ref Target - Figure 4-12
Figure 4-12: Clock Signal from FPGA to Memory (Slow Weak Case)
ug060_c5_13_091003
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