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Instruction Descriptions 4–73
4.7.7.3 Arithmetic Trap Completion
Because floating-point instructions may be pipelined, the trap PC can be an arbitrary number
of instructions past the one triggering the trap. Those instructions that are executed after the
trigger instruction of an arithmetic trap are collectively referred to as the trap shadow of the
trigger instruction.
Marking floating-point instructions for exception completion with any valid qualifier combina-
tion that includes the /S qualifier enables the completion of the triggering instruction. For any
instruction so marked, the output register for the triggering instruction cannot also be one of
the input registers, so that an input register cannot be overwritten and the input value is avail-
able after a trap occurs.
See Section B.2 for more information.
The AMASK instruction reports how the arithmetic trap should be completed:
• If AMASK returns with bit 9 clear, floating-point traps are imprecise. Exception com-
pletion requires that generated code must obey the trap shadow rules in Section
4.7.7.3.1, with a trap shadow length as described in Section 4.7.7.3.2.
• If AMASK returns with bit 9 set, the hardware implements precise floating-point traps.
If the instruction has any valid qualifier combination that includes /S, the trap PC points
to the instruction that immediately follows the instruction that triggered the trap. The
trap shadow contains zero instructions; exception completion does not require that the
generated code follow the conditions in Section 4.7.7.3.1 and the length rules in Section
4.7.7.3.2.
4.7.7.3.1 Trap Shadow Rules
For an operating system (OS) completion handler to complete non-finite operands and excep-
tions, the following conditions must hold.
Conditions 1 and 2, below, allow an OS completion handler to locate the trigger instruction by
doing a linear scan backwards from the trap PC while comparing destination registers in the
trap shadow with the registers that are specified in the register write mask parameter to the
arithmetic trap.
Integer overflow enabled and
inexact disabled
/V
/SV
Imprecise
Precise exception completion
Integer overflow enabled and
inexact enabled
/SVI Precise exception completion
Table 4–9: Summary of IEEE Trapping Modes (Continued)
Trap Mode Notation Meaning