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Instruction Descriptions 4–9
4.2.4 Load Memory Data into Integer Register Locked
Format:
Operation:
va ← {Rbv + SEXT(disp)}
CASE
big_endian_data: va’ ← va XOR 000
2
! LDQ_L
big_endian_data: va’ ← va XOR 100
2
! LDL_L
little_endian_data: va’ ← va ! LDL_L
ENDCASE
lock_flag ← 1
locked_physical_address ← PHYSICAL_ADDRESS(va)
Ra ← SEXT((va’)<31:0>) ! LDL_L
Ra ← (va)<63:0> ! LDQ_L
Exceptions:
Instruction mnemonics:
Qualifiers:
Description:
The virtual address is computed by adding register Rb to the sign-extended 16-bit displace-
ment. For a big-endian longword access, va<2> (bit 2 of the virtual address) is inverted, and
any memory management fault is reported for va (not va’). The source operand is fetched
from memory, sign-extended for LDL_L, and written to register Ra.
LDx_L Ra.wq,disp.ab(Rb.ab)
!Memory format
Access Violation
Alignment
Fault on Read
Translation Not Valid
LDL_L Load Sign-Extended Longword from Memory to Register
Locked
LDQ_L Load Quadword from Memory to Register Locked
None