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B–6 Alpha Architecture Handbook
B.3 Mapping to IEEE Standard
There are five IEEE exceptions, each of which can be "IEEE software trap-enabled" or dis-
abled (the default condition). Implementing the IEEE software trap-enabled mode is optional
in the IEEE standard.
The assumption, therefore, is that the only access to IEEE-specified software trap-enabled
results will be generated in assembly language code. The following design allows this, but only
if such assembly language code has TRAPB instructions after each floating-point instruction,
and generates the IEEE-specified scaled result in a trap handler by emulating the instruction
that was trapped by hardware overflow/underflow detection, using the original operands.
There is a set of detailed IEEE-specified result values, both for operations that are specified to
raise IEEE traps and those that do not. This behavior is created on Alpha by four layers of
hardware, PALcode, the operating-system completion handler, and the user signal handler, as
shown in Figure B–2.
5 Inexact result enable (INEE)
Initiate an INE exception if the result of a floating arithmetic or conversion opera-
tion differs from the mathematically exact result.
4 Underflow enable (UNFE)
Initiate a UNF exception if a floating arithmetic or conversion operation under-
flows the destination exponent.
3 Overflow enable (OVFE)
Initiate an OVF exception if a floating arithmetic or conversion operation over-
flows the destination exponent.
2 Division by zero enable (DZEE)
Initiate a DZE exception if an attempt is made to perform a floating divide opera-
tion with a divisor of zero.
1 Invalid operation enable (INVE)
Initiate an INV exception if an attempt is made to perform a floating arithmetic,
conversion, or comparison operation, and one or more of the operand values is
illegal.
0 Reserved for implementation software.
Table B–1: Floating-Point Control (FP_C) Quadword Bit Summary (Continued)
Bit Description