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11–3
draina Drain all aborts including machine checks
The draina instruction drains all aborts, including machine checks, from the
current processor. Draina guarantees that no abort is signaled for an instruction
issued before the draina while any instruction issued subsequent to the draina is
executing.
dtbis Data translation buffer invalidate single
The dtbis instruction invalidates a single data stream translation. The transla-
tion for the virtual address must be invalidated in all data translation buffers
and in all virtual data caches.
ealnfix Enable alignment fixups
The ealnfix instruction enables alignment fixups in PALcode and prevents
alignment fault exceptions. After ealnfix is executed on a processor, all align-
ment faults on that processor are fixed-up by PALcode and no alignment fault
exceptions are dispatched to the kernel until the dalnfix instruction is executed
on that processor.
ei Enable interrupts
The ei instruction enables interrupts for the IRQL set in the PSR internal pro-
cessor register by setting the interrupt enable (IE) bit in the PSR.
halt Halt the operating system by forcing illegal instruction trap
The halt instruction forces an illegal instruction exception.
initpal Initialize PALcode data structures with operating system values
The initpal instruction is called early in the kernel initialization sequence to
establish values for internal processor registers (IPRs) that are needed for trap
and fault handling. The KGP and PCR registers are initialized once and persist
throughout the run time of the operating system.
initpcr Initialize processor control region data
The initpcr instruction caches process-specific information, including parts of
the interrupt level table (ILT), for use by the PALcode.
rdcounters Read the software event counters
The rdcounters instruction is only used with debug PALcode. With production
PALcode, rdcounters returns a status value of zero, indicating that it is not
implemented in the current PALcode image.
Table 11–2 : Privileged Windows NT Alpha PALcode Instruction Summary (Continued)
Mnemonic Operation and description